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Overview
Mid-Level

AI Silicon Physical Design Engineer

Confirmed live in the last 24 hours

Cerebras Systems

Cerebras Systems

Compensation

$150,000 - $250,000/year

Remote Office; Sunnyvale, CA
Remote
Posted February 17, 2026

Job Description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.  

Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. 

Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

About The Role 

Join our close-knit physical design team where you'll excel in synthesizing, placing, and routing high speed designs. Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture. 

Skills & Qualifications 

  • 10+ years of physical design & physical verification experience. 
  • Strong knowledge of block level and full-chip physical verification methodology. 
  • Strong experience in block/subsystem timing closure.
  • Expert at optimizing for the best power/performance and area.
  • Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus. 
  • Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues. 
  • Expert with IR/EM analysis and resolution.
  • Good understanding of full chip floor planning and integration.  pythongomachine learningaidataproductdesign