Staff Engineer, Digital Verification

Staff Engineer, Digital Verification

 

Company Description

At Butterfly Network, we’re leading a digital revolution in medical imaging, transforming an industry that has long relied on bulky, analog systems. With our proprietary Ultrasound-on-Chip™ technology, we’re democratizing healthcare by shifting ultrasound from the expensive, stationary systems of the past to the connected, mobile, and software-enabled platforms of today.  In 2018, we launched the world’s first handheld, whole-body ultrasound, Butterfly iQ – followed by iQ+ in 2020 and iQ3 in 2024, each more powerful than the last.

Our innovation doesn’t stop at hardware. Butterfly combines our advanced device with intelligent software, AI, services, and education to drive adoption of affordable, accessible imaging. Our technology is proving to help clinicians, clinics, and hospitals enhance care, cut costs, and expand imaging access. We’ve been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions, Fast Company’s World Changing Ideas, among other awards.

We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together!

 

Job Description

The role of the Staff Digital Verification Engineer offers the opportunity to work at the core of the product development team alongside company leadership and founders, helping ensure the correctness and robustness of the digital systems that differentiate Butterfly Network’s products. This individual will be responsible for architecting, developing, and executing comprehensive verification strategies for complex digital signal processing blocks, high-speed interfaces, and large system-on-chip (SoC) designs used in next-generation ultrasound imaging platforms.

As a senior member of the engineering team, you will drive verification methodology, automation, and infrastructure to enable rapid development and high confidence in silicon correctness.

 

Responsibilities

As part of our team, your core responsibilities will include:

• Architect and develop verification environments for large SoC subsystems using Python-based frameworks, primarily Cocotb.
• Design and implement self-checking testbenches, constrained stimulus, scoreboards, and coverage infrastructure.
• Develop bit-accurate reference models (Python) to validate DSP and fixed-point behavior.
• Verify complex digital signal processing blocks, high-speed interfaces, and system-level datapaths.
• Collaborate closely with RTL designers to define verification plans, drive coverage closure, and ensure design correctness.
  Develop and maintain automated regression infrastructure and CI pipelines using GitHub-based workflows.
• Debug functional issues in simulation, emulation, and post-silicon environments.
• Contribute to improving the verification methodology, productivity tools, and infrastructure used across the team.
• Work cross-functionally with architecture, RTL design, firmware, and system teams to ensure robust end-to-end functionality.

Qualifications

• BS/MS/PhD in EE/CE (or equivalent practical experience in digital verification).
• 8+ years (typical Staff level) experience in digital IC / ASIC / SoC verification.
• Strong experience building and maintaining Python-based verification environments, particularly Cocotb.
• Deep knowledge of SystemVerilog and digital design concepts sufficient to effectively verify complex RTL.
• Proven experience verifying large digital IP blocks or SoC subsystems through full verification closure and tapeout cycles.
• Experience building self-checking testbenches, scoreboards, monitors, and stimulus generators.
• Experience developing bit-accurate Python models for algorithm verification and golden reference comparison.
• Strong debugging skills across simulation, waveform analysis, and root-cause analysis of RTL issues.
• Experience building automated regression frameworks and CI workflows using GitHub or similar tools.
• Solid understanding of SoC design challenges including CDC/RDC verification, reset architecture, and power-aware verification.
• Strong cross-func