Principal Engineer, Physical Implementation

Company Description

At Butterfly Network, we’re leading a digital revolution in medical imaging, transforming an industry that has long relied on bulky, analog systems. With our proprietary Ultrasound-on-Chip™ technology, we’re democratizing healthcare by shifting ultrasound from the expensive, stationary systems of the past to the connected, mobile, and software-enabled platforms of today.  In 2018, we launched the world’s first handheld, whole-body ultrasound, Butterfly iQ – followed by iQ+ in 2020 and iQ3 in 2024, each more powerful than the last.

Our innovation doesn’t stop at hardware. Butterfly combines our advanced device with intelligent software, AI, services, and education to drive adoption of affordable, accessible imaging. Our technology is proving to help clinicians, clinics, and hospitals enhance care, cut costs, and expand imaging access. We’ve been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions, Fast Company’s World Changing Ideas, among other awards.

We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together!

Job Description

Qualifications

Baseline skills/experiences/attributes:

• BS/MS/PhD in EE/CE or equivalent physical design experience.
• 8–12+ years (typical Principal level) in physical design (PD) with deep knowledge of industry standards and practices in Physical Design, including physically aware synthesis, Floor-planning, DFT insertion, and Place & Route.
• Experience developing and implementing Power-grids and Clock specifications.
• Strong understanding of Physical construction, Integration and Physical Verification.
• Knowledge of SoC Architecture and HDL languages (Verilog) to interface with logic design team for timing fixes.
• Power user of industry standard Physical Design & Synthesis tools such as Genus, Innovus, Tempus.
• Hands-on expertise in DRC/LVS/DFM closure, including hierarchical LVS debugging, connectivity issues (opens/shorts), and waiver governance.
• Experience with reliability/power integrity signoff (EM/IR fundamentals).
• Proven ability to drive end-to-end signoff, including methodology definition, closure execution, and tapeout release documentation.
• Strong scripting skills (Python, Tcl, or shell) for reproducible flows and metrics dashboards.
• Demonstrated ability to work cross-functionally with front-end designers and IP owners to drive closure and support block-to-top signoff integration.

Ideally, you also have these skills/experiences/attributes (but it’s ok if you don’t!):

• Advanced node experience (16nm or smaller) and associated DFM complexity.
• Experience in regulated / high-reliability products where traceability and signoff rigor are critical.
• Experience with multi-voltage, power-gated, and power-retention designs.
• Practical knowledge of hierarchical design, top-down budgeting, and physical convergence.
• Experience integrating internal/external IP and defining requirements in the physical domain.
• Experience interfacing with foundry/PDK vendors regarding rule updates and signoff collateral alignment.

Values

Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in…

• Patient-Centric Innovators: Our mission is THE mission.
• Empowered to Impact: Every voice matters.
• One Team, One Goal: Unity fuels progress.
• Growth Champions: We embrace challenges.
• Action-Oriented Achievers: We follow through, every time.

Location

Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers.

This is a hybrid position and will be based out of our office in either the Greater SF Bay Area or Burlington, MA. 

Benefits and Perks