Lead Digital Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title:                                             Lead Digital Verification Engineer

Location:                                            Edinburgh

Reports to:                                         Design Engineering Group Director

Job Overview:

The Cadence Silicon Systems Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets.  As a member of the Central Engineering Team within SSG, you will be responsible for defining and supporting the adoption of cutting-edge verification tools and methodologies with a focus on AI and Machine Learning.  You will have a horizontal role working with multiple projects and teams to accelerate adoption of latest verification best practices. 

The Lead Verification Engineer will be based in Edinburgh, Scotland as part of an experienced digital design and verification IP team.

Job Responsibilities:

• Develop and support adoption of generative AI tools to create and update, UVM and Formal verification environments
• Develop methodology guidance and end to end flows to ensure AI tools used in a consistent, efficient and predictable way
• Develop and roll out solutions that reduce verification debug time
• Automate documentation checking to improve quality and consistency
• Build tools and processes to support verification planning
• Optimise UVM regressions through improved automation and machine learning
• Maintain and develop best practices for Functional Safety Verification, Gate Level Simulation and Low Power Verification
• Maintain and improve design review checklists and quality documentation

Job qualifications and required skills:

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
• 4+ years experience in the microelectronics/EDA industry
• Proficiency in System Verilog and assertions
• Hands-on experience with Metric Driven Verification (MDV)
• Strong knowledge of constrained-random verification techniques (e.g. UVM)
• Excellent spoken and written English
• Self-motivated, with strong planning, interpersonal, and communication skills

Additional Skills/Preferences:                     

• Formal verification experience and related applications
• Proficiency with scripting languages (e.g. Python)
• Knowledge of AI agent development (tools, concepts, and infrastructure)
• Methodology development and change management experience
• Familiarity with front-end design tools (e.g. LINT, CDC analysis)
• Exposure to quality processes and standards (e.g. ISO 9001, ISO 26262)

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 

Check what we can offer you:

• Competitive salary
• 25 days holiday per year
• Private Medical and Dental plans, Income Protection and Life Insurance
• Group Personal Pension Plan
• Cycle to work scheme and gym subsidy
• 5 days paid time to volunteer to give back to our communities
• Employee Stock Purchase Plan
• The opportunity to work for a Great Place to Work© & Fortune 100 organization

Travel:   <5%  

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