Job Details:

Job Description:

CEG HIPD MYS is seeking mixed-signal design engineer to join our talented and vibrant team. You will be directly involved in delivering next-generation DDR PHY designs for SOC application on Intel leading process node. Key Responsibilities include but not limited to • Develop a Mixed-Signal Validation (MSV) testbench in accordance with the specified requirements. • Own MSV for Custom Building Blocks (CBB) which covering open loop functional checks, closed-loop functional checks with RTL blocks, PHY level features, high volume manufacturing (HVM) features, closed-loop with Memory Reference Code(MRC) checks. • Independently analyze the result based on specification documents and debug the root cause of the failures. • Participate in MSV result review and collaborate with designers.

Qualifications:

Preferred Qualification:
• Bachelor's or Master's degree in Electronics Engineering.
• Education Focus should include integrated circuit design or RTL design.
• Highly analytical team player with a strong interest in debugging and problem-solving
• Strong written and oral communication skills
• Ability to operate independently and thrive in high-pressure, demanding environments.

          

Job Type:

College Grad

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.