About the role

Aplyr's Quick Take

This role is for a Senior Design Engineering Architect focused on RTL design for PCIe and related technologies. You'll be working on architectural design, feature addition, and verification of complex IP solutions. It's primarily an individual contributor role requiring deep technical expertise in RTL design and experience with various protocols.

Good fit

Ideal candidates have 6-16 years of RTL design experience, particularly with Verilog and System Verilog. A background in VLSI and familiarity with CPU subsystems will help you thrive in this technical environment.

Worth noting

The position emphasizes a strong technical background with a focus on complex protocol implementation, which may be challenging for those without specific experience in PCIe or similar technologies. The company highlights a commitment to impactful work, suggesting a potentially rewarding environment.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

RTL Design Engineer for Interface Controller IP development team.
Position is based in Bangalore or Noida.
The role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems.
The role would also include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.
The work involved will be addition of new features into the RTL, working with existing RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements:

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
6-16 years of core RTL Design experience using Verilog is a must.
System Verilog experience and experience with UVM based environment usage / debugging is required.
Architecture and design of CPU subsystem, including memory subsystem design, IO and cache subsystems is a must.
PCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is desirable.
Prior experience in IP development teams would be an added advantage.
Scripting knowledge is an advantage.

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Skills & Tags

design

Aplyr's read

Cadence Design Systems excels in electronic design automation, attracting professionals passionate about integrated circuits and system-on-chip innovations.
Synthesized from recent postings & public sources

What's promising

•Cadence is a leader in electronic design automation, providing cutting-edge tools for semiconductor design.
•The company offers diverse career paths, from digital verification to automotive solutions engineering.
•Cadence's global presence provides opportunities for international collaboration and growth.

What to watch

•The niche focus on EDA may limit opportunities for those seeking broader tech roles.
•High competition in the semiconductor industry could impact job stability and growth.
•Frequent technical updates require continuous learning, which may be challenging for some employees.

Why Cadence Design Systems

•Cadence's software is integral to designing advanced integrated circuits and systems on chips.
•The company has a strong reputation for innovation in electronic design automation.
•Cadence's partnerships with leading tech firms enhance its influence in the semiconductor industry.

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About Cadence Design Systems

Cadence Design Systems

cadence.com

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Cadence Design Systems provides electronic design automation (EDA) software and engineering services for the design of integrated circuits, systems on chips, and printed circuit boards.