Job Details:

Job Description:

Join our dynamic team as a Physical Design Engineer, where you'll play a pivotal role in delivering cutting-edge custom IP and SoC designs that drive Intel's innovative products. You'll be a key contributor to the physical design flow, ensuring that designs transition seamlessly from RTL to GDS and are optimized for manufacturing. By leveraging your technical expertise, you will directly impact the power, performance, and area of our designs, enabling Intel to maintain its leadership in the semiconductor industry. This position offers an exciting opportunity to work on advanced technology nodes and collaborate with cross-functional teams to develop next-generation solutions.

Key Responsibilities

• Perform physical design implementation of custom IP and SoC designs, from RTL to GDSII finalization.
• Execute tasks in the physical design flow, including floorplanning, synthesis, place and route, clock tree synthesis, and static timing analysis.
• Conduct verification and signoff for formal equivalence, timing, reliability, power integrity, and layout.
• Identify, analyze, and resolve violations in timing, power, and noise to ensure optimal design quality.
• Collaborate on chip partitioning, pin placement, power distribution, and congestion mitigation to optimize physical layouts.
• Utilize and enhance design methodologies and automation flows to improve efficiency and accuracy.
• Leverage industry-standard EDA tools for tasks such as synthesis, routing, and timing closure (e.g., Fusion Compiler, IC Compiler II, PrimeTime).
• Perform ECO (Engineering Change Order) implementation and top-level physical verification signoff.
• Partner with cross-site and cross-functional teams to innovate and deliver results aligned with Intel's strategic goals.

Qualifications:

Minimum Qualifications

• Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of experience, or a Master's degree and 2+ years of experience, or a PhD with no required experience.
• Proficiency in RTL to GDSII tools, including Fusion Compiler, Design Compiler, IC Compiler II, and PrimeTime.
• Strong expertise in physical design workflows, including floor planning, synthesis, place and route, clock tree synthesis, and static timing analysis.
• Hands-on experience with scripting languages such as Python, Perl, and TCL for flow automation.
• In-depth knowledge of hardware description languages such as Verilog or VHDL.
• Familiarity with Unix-based systems and shell scripting.

Preferred Qualifications

• Proven track record of multiple tapeouts in deep submicron technology nodes.
• Experience in DDR design or other high-speed interfaces.
• Background in block-level and full-chip floor planning, power grid design, and power optimization techniques.
• Demonstrated ability to lead key technical initiatives and deliver complex physical databases for ASICs, SoCs, or IPs.
• Strong problem-solving skills with expertise in debugging simulation and verification failures.
• Excellent written and verbal communication skills to collaborate effectively with global teams and stakeholders.

Apply today to be at the forefront of shaping the future of semiconductor technologies with Intel's world-class team.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.