Job Details:

Job Description:

The Role and Impact:
We are seeking a skilled RF Design Engineer to join our innovative team. In this role, you will define, design, and develop complex radio frequency integrated circuits (RFICs) within IPs and SoCs.

Your work will play a pivotal role in shaping next-generation wireless communication technologies, including 5G and 6G.

As an RF Design Engineer, you will collaborate with cross-functional teams to create new product concepts, perform feasibility analyses, and ensure detailed transistor-level designs and validations.

By leveraging your expertise in RF circuit architecture and electromagnetic theory, you will directly contribute to delivering superior products that meet customer needs and industry standards, reinforcing Intel's position as a leader in technology innovation.

Key Responsibilities

• Define, design, and develop RFICs in IPs and SoCs while creating and executing verification test plans for RF validation.
• Conduct transistor-level feasibility analyses, define floorplans, and perform layout for RF circuit architecture.
• Design new product concepts, prototypes, and detailed RF circuit drawings.
• Develop and analyze test procedures, ensuring compliance with applicable codes, standards, and regulations.
• Perform radio signal path designs and detailed transistor-level designs for transceivers and RFIC blocks.
• Apply advanced understanding of electromagnetic theory, communication theory, and RF system analysis to resolve design issues.
• Validate RF system block characterization and specifications, ensuring adherGuide layout practices for deep sub-micron technology to enhance circuit performance and reliability.

Qualifications:

• Master or PhD degree in relevant field with a minimum of 8 years of experience in analog and mixed-signal design with a special focus on ADC and DAC.
• Fundamental understanding of sub-micron device physics and experience in low voltage CMOS RFIC design.
• Familiarity with mixed-signal design validation.
• Ability to analyze and guide layout and knowledge of layout practices for deep sub-micron technology and their impact on circuit performance.

This position is subject to the collective agreement for workers and employees in the electrical and electronics industry, employment group H: https://www.feei.at/wp-content/uploads/2025/09/caeei-2025-08-25.pdf

  

A higher payment is negotiable depending on your expertise and skills.

Prior to entering an employment agreement, the employee will be asked to provide all documents and references to verify any service times of prior employment. Based on provided documents the appropriate number of service years will be credited as prior employment.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Austria)

Primary Location:

Austria, Villach

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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