Senior Verification Engineer

Position Overview 

We are seeking a Senior FPGA Verification Engineer with 4–8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in System Verilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams. 

 Key Responsibilities: 

• Develop and maintain System Verilog/UVM-based verification environments for FPGA block-level and top-level designs  
• Create and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage  
• Perform simulation-based verification of FPGA designs using industry-standard simulators  
• Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers
• Integrate and maintain VIPs, scoreboards, checkers, and reference models  
• Support FPGA bring-up, validation, and debug activities on FPGA platforms and evaluation boards  
• Review FPGA RTL, verification code, and test plans to ensure quality and completeness  
• Mentor junior engineers and contribute to FPGA verification best practices
• Support regression runs, coverage closure, and release signoff 

Qualifications 

Education:  

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 

Experience: 

4–8 years of hands-on experience in functional verification 

Preferred Qualifications:  

• Familiarity with cadence tools like Xcelium 
• Familiarity with Xilinx Vivado 
• Experience with hardware/software co-verification  
• Knowledge of high-speed interfaces (AXI, AXIStream, DDR, SPI)  

Soft Skills: 

• Strong analytical and debugging skills  
• Ability to work effectively in cross-functional teams  
• Excellent written and verbal communication skills  
• Self-driven with the ability to own verification tasks end-to-end  
• High attention to detail and commitment to quality 

Technology Stack: 

• Languages: System Verilog, Verilog, VHDL (working knowledge)  
• Verification Methodology: UVM  
• Simulation Tools: Xcelium, Questa, VCS  
• FPGA Tools: Xilinx Vivado  
• Debug Tools: SimVision  
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