Director of Design Verification (Photonic Fabric™)

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell's Photonic Fabric™ team is building next-generation optical interconnect technology for the era of accelerated computing. As AI workloads scale, the bottleneck has shifted from compute to interconnect bandwidth, memory bandwidth, and memory capacity. Our Photonic Fabric delivers a tenfold improvement in performance and energy efficiency deployed as optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB) that integrate into customers' AI accelerators and GPUs.

This is a rare foundational leadership opportunity to work on cutting edge IP and SoC verification - you'll shape design strategy from the ground up and build a world-class team as part of our strategic expansion into Southern California. You're not joining an established local team - you're building one. You'll hire the engineers, define the culture, establish the methodology, and shape the technical DNA of Marvell's San Diego design verification organization.

What You Can Expect

• Develop SystemVerilog/UVM verification environments for complex SoCs, from block-level IPs through full-chip integration. 

• Create detailed verification plans for block, IP, and SoC-level projects, ensuring comprehensive functional and code coverage. 

• Architect UVM testbenches including stimulus generators, scoreboards, coverage models, and constrained random sequences. 

• Collaborate closely with design, architecture, and software teams to manage milestones and ensure timely deliverables. 

• Drive continuous improvement of verification methodologies and processes across the team. 

• Build and optimize verification infrastructure regression frameworks, coverage tooling, and automation to improve efficiency. 

• Lead rigorous testbench reviews with designers, architects, and software engineers to uphold verification quality.

• Coordinate with software and emulation teams to ensure first-pass tapeout success.

• Use leading edge AI tools to develop infrastructure and environments effectively and efficiently.

What We're Looking For

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 12+ years of relevant experience or Master's degree with 10+ years of experience or PhD with 8+ years of experience.

• Demonstrable experience leading and building robust verification teams.

• Strong proficiency in SystemVerilog with deep expertise in UVM methodology, including constrained random verification, coverage-driven techniques, and UVM library development. 

• Proven track record achieving thorough functional and code coverage closure on complex SoC or IP tapeouts. 

• Solid scripting skills in Python for verification automation, infrastructure, and tooling.

• Experience with industry simulators such as Xcelium, Questa, or VCS.

• Strong experience with object-oriented design and implementation. 

• Excellent communication skills with the ability to collaborate effectively across design, architecture, and software teams. 

• Experience with AI development tools. 

• Experience with protocols such as AMBA (AXI/AHB/APB), PCIe, Ethernet, I2C, SPI, or UART.

• Experience with ARM/processor subsystem verification, memory controllers, NoC, or cache designs. 

• Working knowledge of C/C++ for reference modeling or firmware-driven verification. 

• Familiarity with gate-level simulation and post-silicon validation debug. 

• Experience mentoring junior verification engineers. 

Expected Base Pay Range (USD)

197,400 - 292,150, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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