Application Engineer I: Analog IC Design and Layout

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Application Engineer I: Analog IC Design and Layout to work with us in Belo Horizonte, Brazil.

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

As an Application Engineer, you will be part of Global Customer Success (GCS) - ASK team in Belo Horizonte, Brazil. The ASK team works with Digital, Analog, Verification, Systems tools and provides application support to all Cadence customers. To understand more on our tools & flows, you can visit https://www.cadence.com

Job Responsibilities:

• Support customers in improving productivity using Cadence Virtuoso for analog schematic capture and layout; or in debugging circuit behavior and convergence issues using Spectre, SpectreRF, and/or AMS simulators.
• Learn and apply best practices in analog design flows, including schematic-driven layout, layout-dependent effects, and simulation setup; or help analyze simulation results related to DC, transient, AC, and noise analysis, under guidance from senior AEs.
• Collaborate with senior Application Engineers, R&D, and field teams to reproduce issues, test solutions, and improve tool usability.
• Develop technical documentation, examples, and knowledge content to improve customer self-service and tool adoption.
• Contribute to custom solutions and automation, using scripting and tool capabilities when applicable.

Minimum Requirements:

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related fields.
• Strong foundation in analog electronics (e.g., amplifiers, biasing, MOS device operation).
• Familiarity with CMOS fundamentals and semiconductor device behavior.
• Exposure to circuit simulation concepts (DC, transient, AC analysis).
• Basic experience with EDA environments and Linux-based workflows.
• Strong analytical, debugging, and problem-solving skills.
• Ability to learn complex tool flows and clearly communicate technical findings.

Nice to Have:

• Academic or internship exposure to Cadence Virtuoso (schematic and/or layout).
• Familiarity with Spectre, SpectreRF, or AMS simulation concepts.
• Basic understanding of layout fundamentals (DRC, LVS, parasitics).
• Exposure to mixed-signal or RF concepts.
• Basic scripting knowledge (SKILL, Python, TCL).

Additional Job Details:

• Employment category: CLT.
• Employment term: 40 hours/week
• This position is based in Belo Horizonte, Brazil.
• Competitive benefits.

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.

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