GPU Physical Design Clocking Engineer

Preferred Qualifications

Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence. Experience planning, implementing, and analyzing high-speed clock distribution networks from the root to leaf. Exposure to different strategies for clock distribution including balanced trees, mesh, and forwarded clocks. Ability to use critical clock metrics revolving around latency, skew, and variation to prevent and solve sophisticated cross-hierarchy clocking issues. Experience planning and crafting test structures to evaluate clocking functionality and performance post Silicon. Background in engaging with Test teams pre/post Silicon to debug and analyze problems from a clocking perspective. Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain. Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration. Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies. Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt. Proven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class designs. Understanding of GPU architecture and design units.