About the role

Aplyr's Quick Take

This role is for a Senior Principal Software Engineer focused on developing and enhancing AMBA protocol verification products. You'll be designing features, debugging, and collaborating with teams to ensure performance and scalability. It's an individual contributor role that requires deep technical expertise in digital design and verification.

Good fit

Ideal candidates have strong backgrounds in digital design and system-level verification, with experience in hardware description languages and protocol architectures. You should be comfortable working independently and across teams, and have solid debugging skills.

Worth noting

The role emphasizes collaboration with customers to resolve issues, which might involve direct interaction with clients. The focus on both hardware and software aspects could appeal to those looking for a diverse technical challenge.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview:

This role will contribute directly to the development and enhancement of AMBA Performance verification and/or Unipro stack products, focusing on protocol functionality, performance, and robustness. Depending on the specific protocol area, the work may involve:

Implementing AMBA protocol features and state machines
Enhancing performance and scalability on emulation platforms
Developing debug, trace, and analysis capabilities
Working with customers and field teams to resolve issues and deliver solutions related to AMBA (CHI*, ACE, AXI)

Job Responsibilities:

Designing and implementing protocol functionality in AMBA AVIP
Developing and debugging BFMs, transactors, and associated software interfaces
Ensuring correctness, performance, and scalability in emulation and acceleration flows
Collaborating with cross‑functional teams
Participating in feature bring‑up, regression, and release activities
Supporting customer issues, reproducing problems, and delivering fixes
GUI based performance analysis tool development

Job Qualifications:

Strong fundamentals in digital design, computer architecture, and system‑level verification
Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++
Understanding of standard interconnect and bus architectures (e.g., AMBA, UFS/Unipro/MPhy)
Familiarity with emulation, acceleration, or hybrid verification flows is a strong plus
Good debugging skills using waveforms, logs, and protocol analyzers
Ability to work across hardware and software boundaries

We’re doing work that matters. Help us solve what others can’t.

Aplyr's read

Cadence Design Systems excels in electronic design automation, attracting professionals passionate about integrated circuits and system-on-chip innovations.
Synthesized from recent postings & public sources

What's promising

•Cadence is a leader in electronic design automation, providing cutting-edge tools for semiconductor design.
•The company offers diverse career paths, from digital verification to automotive solutions engineering.
•Cadence's global presence provides opportunities for international collaboration and growth.

What to watch

•The niche focus on EDA may limit opportunities for those seeking broader tech roles.
•High competition in the semiconductor industry could impact job stability and growth.
•Frequent technical updates require continuous learning, which may be challenging for some employees.

Why Cadence Design Systems

•Cadence's software is integral to designing advanced integrated circuits and systems on chips.
•The company has a strong reputation for innovation in electronic design automation.
•Cadence's partnerships with leading tech firms enhance its influence in the semiconductor industry.

Aplyr’s read is generated by AI from public sources. Was it useful?

About Cadence Design Systems

Cadence Design Systems

cadence.com

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Cadence Design Systems provides electronic design automation (EDA) software and engineering services for the design of integrated circuits, systems on chips, and printed circuit boards.